二手 TERADYNE Catalyst #9213380 待售

製造商
TERADYNE
模型
Catalyst
ID: 9213380
Tester PPM / LVM / Vmem (M): 16 Meg Scan memory: Enable Frequency (MHZ): 100 Meg User computer: SUN BLADE 1500 Tester computer: SUN BLADE 2500 64 Digital channel (2) VHFAWG 400 DIFF (2) HF DIG TMS (4) HCU ST Src (7) UBVI 60 (6) AAPU (6) Matrix CATALYST_TH 1 BACKPLANE A #Slot Type Num XptA XptB Name 2 000-000-00 0 # 23 24 EMPTY 3 000-000-00 0 # 21 22 EMPTY 4 000-000-00 0 # 19 20 EMPTY 5 879-792-01 0 # 17 18 TIME CC 6 000-000-00 0 # 15 16 EMPTY 7 949-681-50 0 # 13 14 VHFAWG400 DIFF CC 8 949-672-50 0 # 11 12 VHFDIG CC 9 000-000-00 0 # 9 10 EMPTY 10 949-681-50 0 # 7 8 VHFAWG400 DIFF CC 11 949-672-50 0 # 5 6 VHFDIG CC 14 803-594-00 0 # 25 26 UHFSRC CC 15 803-596-05 0 # 27 28 UWPORT 16 803-595-00 0 # 29 30 UWMM 17 000-000-00 0 # 31 32 EMPTY 18 803-596-05 0 # 33 34 UWPORT 19 803-594-00 0 # 35 36 UHFSRC CC 20 803-594-00 0 # 37 38 UHFSRC CC 21 000-000-00 0 # 39 40 EMPTY 22 000-000-00 0 # 41 42 EMPTY 23 000-000-00 0 # 43 44 EMPTY 1 949-669-00 0 # 3 0 HAS (Left HAS LA669-00) 13 949-668-00 0 # 0 0 CATALYST HAC 12 949-667-00 0 # 0 0 DIF 24 949-669-01 0 # 4 0 HAS (Right HAS LA669-01) END RF_PIPES 1 # pipe-name slot schan description Z8A 15 1 # UWPORT (OSP) Z7A 15 2 # UWPORT (OSP) Z6A 15 3 # UWPORT (OSP) Z5A 15 4 # UWPORT (OSP) Z4A 18 1 # UWPORT (OSP) Z3A 18 2 # UWPORT (OSP) Z2A 18 3 # UWPORT (OSP) Z1A 18 4 # UWPORT (OSP) END RF_CONNECTIONS 1 # RF pipe connections between channel cards # slot schan slot schan 14 1 to 15 5 16 3 to 15 7 19 1 to 18 5 20 1 to 18 6 16 1 to 18 7 END # # Up to 4 Precision AC Card Cages are allowed # PRECISION_AC 1 #Slot Type Num Name 1 949-664-00 0 # VHFDIG MF 2 949-827-00 0 # VHFAWG 3 000-000-00 0 # EMPTY 4 949-664-00 0 # VHFDIG MF 5 949-827-00 0 # VHFAWG 6 000-000-00 0 # EMPTY 7 000-000-00 0 # EMPTY 8 949-671-01 0 # PACS CAGE INT END PRECISION_AC 2 #Slot Type Num Name 1 000-000-00 0 # EMPTY 2 000-000-00 0 # EMPTY 3 000-000-00 0 # EMPTY 4 000-000-00 0 # EMPTY 5 000-000-00 0 # EMPTY 6 000-000-00 0 # EMPTY 7 000-000-00 0 # EMPTY 8 949-671-01 0 # PACS CAGE INT END # # Up to 8 Universal Backplane/Synch Power Subsystem # cages are allowed # # For the Synch Power Subsystem: # Slot Type Name Instr1 # Instr2 # Ammeter # # # Instr1 # - insrument connected to the first two matrix lines # Instr2 # - insrument connected to the last two matrix lines # Ammeter # - ammeter connection # to AVOID errors, put NO 0 if no instrument is connected. # # UB_SPS_CAGE 1 # Slot Type Num Name 1 879-802-02 0 # UB_SPS_802 2 517-301-00 0 # UB_APU 3 517-301-01 0 # UB_MATRIX 4 517-301-01 0 # UB_MATRIX 5 517-301-00 0 # UB_APU 6 517-301-00 0 # UB_APU 7 517-301-00 0 # UB_APU 8 517-301-01 0 # UB_MATRIX 9 517-301-01 0 # UB_MATRIX 10 517-301-01 0 # UB_MATRIX 11 517-301-01 0 # UB_MATRIX 12 517-301-00 0 # UB_APU 13 517-301-00 0 # UB_APU 14 879-925-01 0 # UB_60_V_SRC MAT 1 15 879-925-01 0 # UB_60_V_SRC DUT 1 17 879-925-01 0 # UB_60_V_SRC DUT 5 18 879-925-01 0 # UB_60_V_SRC DUT 6 19 879-925-01 0 # UB_60_V_SRC DUT 7 20 879-925-01 0 # UB_60_V_SRC DUT 8 21 879-690-00 0 # UB_ASY 22 517-300-01 0 # UB_TJ300 END HSD100_CHAN_CAGE 1 #Slot Type Num Fld1 Fld2 Name 1 949-921-01 0 # HSD CDM 400 2 949-921-01 0 # HSD CDM 400 3 949-921-01 0 # HSD CDM 400 4 949-921-01 0 # HSD CDM 400 5 949-920-10 0 # HSD CSB END CATALYST_TH 1 BACKPLANE B #Slot Type Num Name 61 949-625-00 0 # HSD DTH 62 949-625-00 0 # HSD DTH 63 949-625-00 0 # HSD DTH 64 949-625-00 0 # HSD DTH 65 949-626-00 0 # HSD THS 66 949-625-00 0 # HSD DTH 67 949-625-00 0 # HSD DTH 68 949-625-00 0 # HSD DTH 69 949-625-00 0 # HSD DTH END # # Trigger Switch Yard # # # # Logical TSY slot (below) Physical slot # 1 -> 2 # 3 -> 1 # TSY CAGE #Slot Type Num Name 1 879-655-02 0 # TSY 2 000-000-00 0 # EMPTY 3 000-000-00 0 # EMPTY 4 000-000-00 0 # EMPTY END # # Time Subsystem # TIME_SUBSYSTEM # Board ID Name 879-793-00 # TMS Timer 879-794-01 # TMS Counter 879-795-01 # TMS Support END # # DC Subsystem - # # SRC <NUM> [1 - 13] # (sources 1-5 are MATRIX sources 1-5 # sources 6-13 are DUT sources 1-8) # HCU <NUM> *[1 - 4] # REF HCU <NUM> *[1 - 4] # HVSRC <NUM> *[1 - 4] # PWRSRC <NUM> [1 - 4] # DATABITS <NUM> - <NUM> [1 - 192] # # ** These instruments share the same seven-slot cage -- only one # instrument is allowed per slot. # DC_SUBSYSTEM # UBVI 60 1 ( 60V V/I Source in Universal Backplane 1 : slot 14) SRC 2 HCU 4 # UBVI 60 6 ( 60V V/I Source in Universal Backplane 1 : slot 15) HCU 7 HCU 8 HCU 9 # UBVI 60 10 ( 60V V/I Source in Universal Backplane 1 : slot 17) # UBVI 60 11 ( 60V V/I Source in Universal Backplane 1 : slot 18) # UBVI 60 12 ( 60V V/I Source in Universal Backplane 1 : slot 19) # UBVI 60 13 ( 60V V/I Source in Universal Backplane 1 : slot 20) DATABITS 1 - 48 # UB_MATRIX # # Testhead 1 # XPTs UB Cage Slot Type # 1-4 1 2 APU # 5-8 1 3 Matrix # 9-12 1 4 Matrix # 13-16 1 5 APU # 17-20 1 6 APU # 21-24 1 7 APU # 25-28 1 8 Matrix # 29-32 1 9 Matrix # 33-36 1 10 Matrix # 37-40 1 11 Matrix # 41-44 1 12 APU # 45-48 1 13 APU END Checker Channels Executions Passes Fails % % Name Brief Full Total Pass Fail MAINFRAME UBST N/A 1 0 1 1 0 100.00 0.00 DCST N/A 1 0 1 1 0 100.00 0.00 MATRIXST N/A 1 0 1 1 0 100.00 0.00 STATIONST N/A 1 0 1 1 0 100.00 0.00 UBAPUST N/A 1 0 1 1 0 100.00 0.00 APUST N/A 0 0 0 0 0 0.00 0.00 ASYST N/A 0 0 0 0 0 0.00 0.00 HCUST N/A 1 0 1 1 0 100.00 0.00 APXFERLINST N/A 0 0 0 0 0 0.00 0.00 PWRVIST N/A 0 0 0 0 0 0.00 0.00 OVIST N/A 0 0 0 0 0 0.00 0.00 TEST HEAD 1 DATABUS_ST N/A 1 0 1 1 0 100.00 0.00 HEADST N/A 1 0 1 1 0 100.00 0.00 UBASYST N/A 1 0 1 1 0 100.00 0.00 HSCST N/A 0 0 0 0 0 0.00 0.00 TURBOACST N/A 0 0 0 0 0 0.00 0.00 TMSALST N/A 1 0 1 1 0 100.00 0.00 PMMST N/A 0 0 0 0 0 0.00 0.00 TRGST N/A 1 0 1 1 0 100.00 0.00 TMEMDLYST N/A 0 0 0 0 0 0.00 0.00 HSD_ST 64 1 0 1 1 0 100.00 0.00 TJDST N/A 0 0 0 0 0 0.00 0.00 BBACST N/A 0 0 0 0 0 0.00 0.00 PACSII_AMS_ST N/A 1 0 1 1 0 100.00 0.00 HFSAMPALST N/A 0 0 0 0 0 0.00 0.00 UHFCWST 3 1 0 1 0 1 0.00 100.00 MODSRCST N/A 0 0 0 0 0 0.00 0.00 UWST 2 1 0 1 0 1 0.00 100.00 VHFCWST N/A 0 0 0 0 0 0.00 0.00 VHFMMST N/A 0 0 0 0 0 0.00 0.00 VHFST N/A 1 0 1 0 1 0.00 100.00 VHF_AMS_ST N/A 1 0 1 0 1 0.00 100.00 GIGADIGST N/A 0 0 0 0 0 0.00 0.00 MODCLK_ST N/A 0 0 0 0 0 0.00 0.00 OVIDCCST N/A 0 0 0 0 0 0.00 0.00 PLFALST N/A 0 0 0 0 0 0.00 0.00 PLF_AMS_ST N/A 0 0 0 0 0 0.00 0.00 LFACST N/A 0 0 0 0 0 0.00 0.00 LFAC_AMS_ST N/A 0 0 0 0 0 0.00 0.00 VREGST N/A 0 0 0 0 0 0.00 0.00 RDC24ST N/A 0 0 0 0 0 0.00 0.00 LCAST N/A 0 0 0 0 0 0.00 0.00 SBCC_ST N/A 0 0 0 0 0 0.00 0.00 QVSDCCST N/A 0 0 0 0 0 0.00 0.00 QVSST N/A 0 0 0 0 0 0.00 0.00 GAZELLE_ST N/A 0 0 0 0 0 0.00 0.00.
TERADYNE Catalyst是為前沿生產測試應用而設計的先進的最終測試設備。它由測試系統和解決方案的領先供應商TERADYNE開發,以滿足芯片制造商最苛刻的要求。Catalyst系統支持一系列平臺,並量身定制,以滿足半導體制造商在快節奏環境中的具體需求。它為生產測試應用程序提供廣泛的功能,並通過其自動化測試過程提供可靠的結果。TERADYNE Catalyst單元由處理器板、測試板、外部測試板、數字I/O模塊和通信組成。處理器板控制測試和測試數據收集的執行,並處理測試執行和設置的時間安排。測試板生成信號並提供對被測設備(DUT)進行廣泛測試的能力。外部板用於將測試功能擴展到機器之外。數字I/O模塊用於向DUT傳送和捕獲數字測試信號。最後,Catalyst工具包括一個高速通信接口,可與外部系統和工具進行通信。TERADYNE Catalyst資產是一種功能強大、全面的測試解決方案,可提供卓越的性能和可靠性。通過減少測試設置時間和利用最新的測試技術,可以提供卓越的測試效率。催化劑模型旨在提供高精度和可重復性,其功能允許在生產過程中快速檢測和糾正產品故障。設備具有先進的診斷功能,可幫助識別和快速隔離有缺陷的設備,從而減少退回設備的數量並降低成本。此外,利用綜合數據收集能力,該系統可以收集統計過程控制數據,以監測生產趨勢並協助進行產量分析。TERADYNE Catalyst單元為要求最苛刻的芯片測試提供了卓越的可擴展性和靈活性。它易於安裝和維護,為大批量生產測試要求提供了經濟高效、可靠的解決方案。
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